The present invention relates to a square computation circuit, and more particularly, to an apparatus for computing the branch evaluation values within a Viterbi decoder in the trellis-coded modulation (TCM) method which is the combination of coding and modulating methods for correcting errors produced on a digital transmission channel.
The Viterbi decoder used in the TCM method has to compute the branch evaluation values by the euclidean distance between the symbol to be decoded and the transferred symbol.
In order to compute the euclidean distance between two symbols, a process of computing the square of data is necessary. Typically, since the TCM method is embodied by means of a digital signal processor, a multiplier is used in the square computation process, as illustrated in FIG. 1. The implementation of the trellis coded modulation method using a digital signal processor is disclosed in the papers entitled "Single DSP Implementation of a High Speed Echo Canceling Modem Employing Trellis Coding" (see Proceedings of the International ESA Workshop on DSP Techniques Applied to Space Communications, November 1988, by A. Fagon et al.) and "Convolutional Encoding and Viterbi Decoding Using the DSP 56001 with a V.32 Modem Trellis Example" (by Dion D. Messer of Motorola, 1989). It is proper to use a multiplier in computing the multiplication of general data, but the computation of the square is a specific case of multiplication computation. Therefore, it is desirable to use a multiplication circuit embodied exclusively for computing the square.